Xilinx spartan, 7 fpga xc7s25, 1csga225c 3, 650 slices containing four 6, Input luts and 8 flip, Flops1, 620 kbits of fast block ramthree clock management tile, Each with a phase, Locked loop and mixed, Mode clock manager80 dsp slicesinternal clock speeds exceeding 450 mhzon, Chip analog, To, Digital converter xadc programmable over jtag and quad, Spi flashmemory 4 mb quad, Spi flashpowered from usb or 5v external supply connected to dip pin 24 micro usb cable not included usb, Jtag programming circuitryusb, 4 leds, Uart bridge2 buttons, 1 rgb led1 pmod connector, 8 total fpga i/o48, Pin dip form, Factor headers 36 populated pins, 32 total fpga i/o, 2 single, Ended 0, 3. 3v analog inputs to xadc